Self-aligned field effect transistor process
US4419810A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 30, 1981 |
| Grant date | Dec 13, 1983 |
| Priority date | — |
| Expiry date | Dec 30, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor [integrated circuit] structure having a sub-micrometer gate length field effect transistor device is described. An isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor within the substrate from one another. Certain of these semiconductor regions are designated to contain field effect transistors [devices]. A heavily doped conductive layer and an insulator layer are formed thereover. The multilayer structure is etched to result in a patterned conductive layer having substantially vertical sidewalls. The pattern of the conductive layer is chosen to be located above the planned source/drain regions with openings in the pattern at the location of the field effect transistor channel. The pattern in the source/drain areas extend over the isolation pattern. A controlled sub-micrometer thickness insulating layer is formed on these vertical sidewalls. The sidewall insulating layer is utilized to controllably reduce the channel length of the field effect transistor. [The sidewall layer is preferably doped with conductive imparting impurities.] The gate dielectric is formed on the channel surface. The sou…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.