CMOS Source/drain implant process without compensation of polysilicon doping
US4420344A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 1981 |
| Grant date | Dec 13, 1983 |
| Priority date | — |
| Expiry date | Oct 15, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/859
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
CMOS source/drain regions of both conductivity types are formed using only a single masking step. One dopant is applied to both types of source/drain regions, and a second dopant is applied at a much higher dose and energy to only one type of source/drain region. Preferably, boron and arsenic are used as the dopants in silicon, since the cooperative diffusion effect causes the boron in the counterdoped source/drain regions to be entirely contained within the arsenic diffusion. To avoid the erratic etching characteristics of heavily-doped polysilicon under chloro-etch, the patterned photoresist used to pattern the gates and gate-level interconnects is left in place during the P+ source/drain implant. Thus, moderately doped N-type polysilicon may be used, since it is not exposed to compensation by the P+ implant. Since no P+ source/drain mask is required, no double-level photoresist structure is created, and there is consequently no obstacle to reworks. In addition, positive resists may be used in practicing the present invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.