Method to fabricate stud structure for self-aligned metallization
US4424621A · kind A · utility
31Cited by
9References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1981 |
| Grant date | Jan 10, 1984 |
| Priority date | — |
| Expiry date | Dec 30, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A self-aligned metal process is described which achieves self-aligned metal silicon contacts and micron-to-submicron contact-to-contact and metal-to-metal spacing by use of the pattern of dielectric material having a thickness in the order of a micron or less. The pattern of recessed oxide isolation to device area is also self-aligned by this process. The process results in substantially planar integrated circuit structure. The process is applicable to either a bipolar integrated circuit either bipolar or MOS field effect transistor integrated circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.