Method of mounting a semiconductor element for analyzing failures thereon
US4431967A · kind A · utility
29Cited by
1References
1Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 21, 1980 |
| Grant date | Feb 14, 1984 |
| Priority date | — |
| Expiry date | Aug 21, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor chip having its main face coated with an electrically insulating film is encapsulated in a plastic, electrically conducting member disposed on a metallic plate so that the surface of the insulating member is exposed and parallel to the metallic plate. The surface of the insulating film is observed by an optical microscope through a nematic liquid crystal film and a glass slide with a transparent, electrically conducting coating successively disposed on the chip with a DC voltage applied between the conducting coating and the metallic plate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.