ECL Compatible CMOS memory
US4437171A · kind A · utility
39Cited by
1References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 7, 1982 |
| Grant date | Mar 13, 1984 |
| Priority date | — |
| Expiry date | Jan 7, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09448
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
CMOS buffers are described which provide compatibility between a CMOS circuit and ECL circuits. The input buffer includes a comparator referenced to the V.sub.BB potential. This potential is developed on the CMOS chip with bipolar transistors integrally formed during the CMOS processing. The output buffer also utilizes a bipolar transistor and includes overshoot protection circuitry to prevent overshooting in the transition on the output line from a high potential to a low potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.