Planar doped barrier gate field effect transistor
US4442445A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 1981 |
| Grant date | Apr 10, 1984 |
| Priority date | — |
| Expiry date | Nov 23, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/17
Abstract
Disclosed is an epitaxial layer field effect transistor having a planar dd barrier gate formed on an n-type semiconductor planar channel region between drain and source terminals formed on the surface of the channel region. The semiconductor channel region is fabricated on a semiconductor substrate, preferably GaAs and being separated therefrom by one or more semiconductor planar buffer regions. The planar doped barrier gate comprises an n.sup.+ -.pi.-p.sup.+ -.pi. structure grown by molecular beam epitaxy over the n-type channel region. Application of an electrical potential to the gate modulates the channel charge depletion in the semiconductor channel region underlying the gate causing a variation in the channel conductance laterally between the source and drain terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.