Non-inverting non-volatile dynamic RAM cell
US4446535A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1981 |
| Grant date | May 1, 1984 |
| Priority date | — |
| Expiry date | Dec 31, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C14/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention provides improved non-volatile semiconductor memories which form non-inverting signals and which include a one device dynamic volatile memory circuit having a storage capacitor which includes a conductive plate, a charged floating gate and an inversion layer in a semiconductor substrate together with a non-volatile device including the floating gate, a control electrode and a voltage divider having first and second serially-connected capacitors, with the floating gate being disposed at the common point between the first and second capacitors. The plate of the storage capacitor is connected to a reference voltage source. The control electrode is capacitively coupled to the floating gate through the first capacitor which includes a charge or electron injector structure. The capacitance of the first capacitor has a value, preferably, substantially less than that of the second capacitor which is formed between the floating gate and the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.