Gary D. Grise
23Patents
7h-index
28Co-inventors
69Inventor score
Filing activity: Jan 2, 1981 → May 11, 2012
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US4870470A | Non-volatile memory cell having Si rich silicon nitride charge trapping layer | Electricity | 323 | Expired |
| US6025992A | Integrated heat exchanger for memory module | Electricity | 70 | Expired |
| US7620921B2 | IC chip at-functional-speed testing with process coverage evaluation | Physics | 23 | Active |
| US5663806A | Non-destructive target marking for image stitching | Electricity | 21 | Expired |
| US7240266B2 | Clock control circuit for test that facilitates an at speed structural test | Physics | 14 | Expired |
| US4375085A | Dense electrically alterable read only memory | Physics | 12 | Expired |
| US4446535A | Non-inverting non-volatile dynamic RAM cell | Physics | 7 | Expired |
| US7856607B2 | System and method for generating at-speed structural tests to improve process and environmental parameter space coverage | Physics | 7 | Active |
| US7996807B2 | Integrated test waveform generator (TWG) and customer waveform generator (CWG), design structure and method | Physics | 7 | Active |
| US8423847B2 | Microcontroller for logic built-in self test (LBIST) | Physics | 5 | Active |
| US7721170B2 | Apparatus and method for selectively implementing launch off scan capability in at speed testing | Physics | 5 | Active |
| US7490280B2 | Microcontroller for logic built-in self test (LBIST) | Physics | 5 | Active |
| US7840864B2 | Functional frequency testing of integrated circuits | Electricity | 5 | Active |
| US8205124B2 | Microcontroller for logic built-in self test (LBIST) | Physics | 3 | Active |
| US7290191B2 | Functional frequency testing of integrated circuits | Electricity | 3 | Expired |
| US7685542B2 | Method and apparatus for shutting off data capture across asynchronous clock domains during at-speed testing | Physics | 3 | Active |
| US7779375B2 | Design structure for shutting off data capture across asynchronous clock domains during at-speed testing | Physics | 3 | Active |
| US8538718B2 | Clock edge grouping for at-speed test | Physics | 2 | Active |
| US7529294B2 | Testing of multiple asynchronous logic domains | Physics | 2 | Active |
| US7840863B2 | Functional frequency testing of integrated circuits | Electricity | 2 | Active |
| US7698611B2 | Functional frequency testing of integrated circuits | Electricity | 1 | Active |
| US7793176B2 | Method of increasing path coverage in transition test generation | Physics | 0 | Active |
| US7784000B2 | Identifying sequential functional paths for IC testing methods and system | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.