Byte-wide dynamic RAM with multiplexed internal buses

US4449207A · kind A · utility

Assignee

• Intel Corporation · US

Inventors

• Roger I. Kung · Beaverton, US
• Stephen T. Flannagan · Austin, US
• Jonathan Spitz · Leonberg, DE
• Perry H. Pelley · Austin, US
• Robert S. Riley · Gaston, US
• Douglas J. Covert · Beaverton, US

Key dates

• Filing date: Apr 29, 1982
• Grant date: May 15, 1984
• Expiry date: Apr 29, 2002

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C5/066
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An MOS dynamic RAM organized in a byte-wide arrangement is described. An internal bus is used for multiplexed column address signals and data. Other multiplexing reduced the lines associated with the input/output circuits. A unique power-on circuit automatically resets clock generators if they are not operative after power is applied.