Stephen T. Flannagan
42Patents
18h-index
25Co-inventors
81Inventor score
Filing activity: Oct 1, 1980 → Nov 29, 2001
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5440514A | Write control for a memory using a delay locked loop | Physics | 130 | Expired |
| US4807191A | Redundancy for a block-architecture memory | Physics | 129 | Expired |
| US5402389A | Synchronous memory having parallel output data paths | Physics | 100 | Expired |
| US5440515A | Delay locked loop for detecting the phase difference of two signals having different frequencies | Physics | 88 | Expired |
| US5384737A | Pipelined memory having synchronous and asynchronous operating modes | Physics | 65 | Expired |
| US4449207A | Byte-wide dynamic RAM with multiplexed internal buses | Physics | 63 | Expired |
| US6157583A | Integrated circuit memory having a fuse detect circuit and method therefor | Physics | 58 | Expired |
| US4698788A | Memory architecture with sub-arrays | Physics | 46 | Expired |
| US5477176A | Power-on reset circuit for preventing multiple word line selections during power-up of an integrated circuit memory | Electricity | 45 | Expired |
| US5268866A | Memory with column redundancy and localized column redundancy control signals | Physics | 42 | Expired |
| US4644196A | Tri-state differential amplifier | Physics | 33 | Expired |
| US4468759A | Testing method and apparatus for dram | Physics | 31 | Expired |
| US4658381A | Bit line precharge on a column address change | Physics | 31 | Expired |
| US5610543A | Delay locked loop for detecting the phase difference of two signals having different frequencies | Physics | 28 | Expired |
| US4406013A | Multiple bit output dynamic random-access memory | Physics | 24 | Expired |
| US4547867A | Multiple bit dynamic random-access memory | Physics | 22 | Expired |
| US5670815A | Layout for noise reduction on a reference voltage | Electricity | 20 | Expired |
| US4636991A | Summation of address transition signals | Physics | 19 | Expired |
| US5426381A | Latching ECL to CMOS input buffer circuit | Electricity | 16 | Expired |
| US4661931A | Asynchronous row and column control | Physics | 15 | Expired |
| US4716302A | Identity circuit for an integrated circuit using a fuse and transistor enabled by a power-on reset signal | Electricity | 15 | Expired |
| US4453237A | Multiple bit output dynamic random-access memory | Physics | 15 | Expired |
| US4630239A | Chip select speed-up circuit for a memory | Physics | 14 | Expired |
| US5293081A | Driver circuit for output buffers | Physics | 14 | Expired |
| US5059829A | Logic level shifting circuit with minimal delay | Electricity | 13 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.