Substrate bias generating circuit
US4455628A · kind A · utility
25Cited by
0References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 4, 1982 |
| Grant date | Jun 19, 1984 |
| Priority date | — |
| Expiry date | Nov 4, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure described a substrate bias generating circuit in which an internal RAS (Row Address Strobe) signal and an internal CAS (Column Address Strobe) signal, both of which are synchronized with an external RAS signal and external CAS supplied from outside in addition to self-oscillator, activate circuits comprising capacitors and rectifying elements respectively so as to reduce wattage dissipation thereof during holding time of RAM and be obtained increased charge pump current during operation thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.