Semiconductor integrated circuit device with low power consumption in a standby mode using an on-chip substrate bias generator
US4460835A · kind A · utility
72Cited by
5References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 6, 1981 |
| Grant date | Jul 17, 1984 |
| Priority date | — |
| Expiry date | May 6, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/096
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A mode switching transistor which is controlled by a chip enable signal is connected between a power supply terminal and a MOS inverter including transistors. The transistor functions as a weak depletion or depletion type MOS transistor to provide sufficient current with a first back gate bias given in an active mode and functions as a perfect enhancement type transistor to completely cut off current with a second back gate bias given in a standby mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.