Semiconductor memory devices
US4460998A · kind A · utility
24Cited by
3References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 1982 |
| Grant date | Jul 17, 1984 |
| Priority date | — |
| Expiry date | Mar 8, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/785
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In addition to a main memory device a spare memory device is provided. Both memory devices utilize word wires in common which are arranged to constitute matrix circuits together with groups of bit lines. When a bit error is contained in data read out from the main memory device, a correction circuit correcting the error and a register for storing the error are provided. An output of the register is used to switch a bit line from which the error has been detected to a corresponding bit line of the spare memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.