Layered metal film structures for LSI chip carriers adapted for solder bonding and wire bonding
US4463059A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1982 |
| Grant date | Jul 31, 1984 |
| Priority date | — |
| Expiry date | Jun 30, 2002 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/12882
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The top surface metallurgy of LSI chip carriers is improved by multiple and phased interface of metal layers which enable such metallurgies to be suitable for joining by solder reflow and wire bonding techniques. The modifications result in separating the solder bonding metallurgy from the fan-out conductor metallurgy with an intermediate layer of a metal such as Cr or Ti which prevents the formation of intermetallic alloys which are mechanically weak or brittle and tend to fracture because of thermal fatigue stresses caused by thermal cycling during either multiple (up to 50) solder bonding reflow operations or operation of the circuit. The fan-out metallurgy conductors are preferably composed of Cr-Cu-Cr layers covered by at least one upper metal layer which is separated from the Cu of the conductor by means of a metal such as phased layers of Cr or Ti deposited before the other upper metal layer or layers. Solder ball bonding surfaces are composed of additional metal in the form of Au, Cu and Ni. The solderless bonding surfaces are composed of a metal selected from Au, Cr, Ti, Al and Co.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.