Semiconductor memory device
US4466081A · kind A · utility
287Cited by
4References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 13, 1981 |
| Grant date | Aug 14, 1984 |
| Priority date | — |
| Expiry date | Nov 13, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is constituted by a MOS transistor having a floating gate for storing data. An erase gate, a portion of which is under a part of the floating gate, is arranged on the MOS transistor to discharge electrons from the floating gate. The MOS transistors are arranged in a matrix form in which the erase gates of all the MOS transistors are commonly connected and a data erase voltage is applied to the erase gates to erase the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.