Testing method and apparatus for dram
US4468759A · kind A · utility
31Cited by
1References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 3, 1982 |
| Grant date | Aug 28, 1984 |
| Priority date | — |
| Expiry date | May 3, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for testing an MOS, dynamic random-access memory employing full capacitance dummy cells is described. During probe testing a potential higher than the reference potential is applied to the dummy cells when reading binary zeroes from the memory and a potential lower than the reference potential is applied to the dummy cells when reading binary zeroes from the memory. This testing procedure detects weak cells and amplifiers and helps present the packaging of defective parts. In addition, a simplified means for programming redundant elements is described which requires substantially less substrate area than previous methods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.