Patent · US Expired

Method for representing logical status changes of a plurality of adjacent circuit nodes in an integrated circuit in a logic image employing a pulsed electron probe

US4471302A · kind A · utility

5Cited by

4References

3Claims

0Family size

Assignee

Siemens Aktiengesellschaft · DE

Inventors

Peter Fazekas · Munich, DE
Hans-Peter Feuerbaum · Hersbruck, DE
Ulrich Knauer · Munich, DE
Johann Otto · Munich, DE

Key dates

Filing date	Jan 20, 1982
Grant date	Sep 11, 1984
Priority date	—
Expiry date	Jan 20, 2002

Classification

Technology area (CPC B)Performing Operations; Transporting
CPC primaryB82Y15/00
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A method for representing logic changes of state occurring at a plurality of adjacent circuit nodes in an integrated circuit in the form of a logic image employs a pulsed electron probe which always scans a same path in the x-direction on the integrated circuit and the phase of the electron pulses comprising the pulsed electron probe is continuously shifted for each new scanning operation. The integrated circuit can be imaged up to the edge of a recording or field of view limit and it is only at this limit that the y-deflection of the pulsed electron probe is fixed. Very small spacings, such as those occurring between adjacent integrated circuit tracks, can thus be reliably imaged on the picture screen of the scanning electron microscope.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.