Process for fabricating GaAs FET with ion implanted channel layer
US4473939A · kind A · utility
9Cited by
6References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 1982 |
| Grant date | Oct 2, 1984 |
| Priority date | — |
| Expiry date | Dec 27, 2002 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/909
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is herein described a process for fabricating GaAs FETs with an ion implanted channel layer wherein an ion implanted substrate is capless annealed under an arsine overpressure, and a relatively shallow portion of the outer surface of the substrate in the active layer is removed for the deposition of a gate metallic electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.