Silicide contacts for CMOS devices
US4476482A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 1982 |
| Grant date | Oct 9, 1984 |
| Priority date | — |
| Expiry date | May 13, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/859
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the manufacture of a CMOS device, oxide is etched away from polysilicon gate-level interconnects, and from source or drain regions of either conductivity type to which the polysilicon gate-level interconnect is desired to be connected. A metal is then deposited, and silicide is formed to connect the gate-level interconnect to the respective source and drain regions. To ensure continuity of the silicide connection, the gate oxide beneath the gate level interconnect is slightly undercut by a wet etching process, additional polysilicon is deposited conformally overall, and the additional polysilicon is anisotropically etched so that it is removed from all areas except those within the undercut region beneath the gate-level interconnect thus a continuous surface of silicon, from which a continuous layer of silicide is then grown, exists between the polysilicon gate-level interconnect and the respective source and drain regions. Thus, self-aligned contacts are created, and no unwanted pn junctions are created.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.