Method for manufacturing semiconductor Bi-CMOS device

US4484388A · kind A · utility

Assignee

• Tokyo Shibaura Denki Kabushiki Kaisha · JP

Inventor

• Hiroshi Iwasaki · Yokohama, JP

Key dates

• Filing date: Jun 14, 1983
• Grant date: Nov 27, 1984
• Expiry date: Jun 14, 2003

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/401

Abstract

A method for forming a Bi-CMOS structure, wherein a vertical npn transistor and CMOS transistors are formed on a single semiconductor substrate, is disclosed. After forming a p-type epitaxial silicon layer on a p-type silicon substrate with a plurality of n.sup.+ -type buried layers therein, n-type wells are formed to extend to the n.sup.+ -type buried layers. Selective oxidation is performed to form field oxide films so as to define an n-type element region for the npn transistor, an n-type element region for the p-channel MOS transistor, and a p-type element region for the n-channel MOS transistor. An oxide film as a gate oxide film for the CMOS is formed on the surfaces of all the element regions. After forming a p-type active base region of the npn transistor by ion-implantation of boron, an emitter electrode comprising an arsenic-doped polysilicon layer is formed in contact with the p-type active base region. Gate electrodes of the CMOS are formed and have a low resistance due to doping with phosphorus and/or arsenic. Using the emitter electrode as a diffusion source, an n-type emitter region is formed. Boron is then ion-implanted to simultaneously form a p.sup.+ -type externa…