Complementary transistor structure and method for manufacture
US4485552A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 1982 |
| Grant date | Dec 4, 1984 |
| Priority date | — |
| Expiry date | Jul 19, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/673
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method of making on a common substrate complementary vertical NPN and PNP transistors having matched high performance characteristics. A barrier region of a first conductivity type is formed on a semiconductor substrate of a second conductivity type. Then, a collector region for one of the complementary transistors of a second conductivity type is formed within the barrier region. It is convenient to simultaneously form isolation regions of a second conductivity type in the substrate while forming the collector region. A collector region of a first conductivity type is then formed in the substrate for the other of the complementary transistors. An epitaxial layer of semiconductor material doped with ions of the first conductivity type is then formed on the surface of the substrate. In a preferred embodiment the P-type emitter for the PNP transistor is formed prior to a last drive-in treatment by forming a polycrystalline silicon layer on the exposed surface of the base. The polycrystalline silicon is doped with a P-type dopant. Thereafter the transistor structure is subjected to conditions whereby the doping ions contained in the polycrystalline silicon layer are dri…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.