Zero drain overlap and self aligned contact method for MOS devices

US4486943A · kind A · utility

Assignee

• Inmos Limited · GB

Inventors

• William Dennis Ryden · Colorado Springs, US
• Matthew Vernon Hanson · Orange, US
• Gary F. Derbenwick · Colorado Springs, US
• Alfred P. Gnadinger · Colorado Springs, US
• James R. Adams, Jr. · Littleton, US

Key dates

• Filing date: Mar 12, 1984
• Grant date: Dec 11, 1984
• Expiry date: Mar 12, 2004

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/60
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The invented technique permits the gate length to equal the channel length: source/drain regions are self-aligned and non-overlapping with respect to their gate electrode. The non-overlapping feature, along with other optimized device characteristics, are generally provided by defining a gate electrode over a substrate, forming an implant mask of dielectric, for example, on the sides of the gate electrode, and implanting a source/drain region such that the implant mask shields a portion of the substrate from implantation to provide a gap between a side edge of the gate electrode and the implanted regions. The source/drain region is then heat driven until its side edge is substantially aligned with the edge of the gate electrode. Self-aligned source/drain contacts are also provided using the implant mask to isolate the gate electrode from the contacts and interconnects.