Electrical partitioning scheme for improving yields during the manufacture of semiconductor memory arrays
US4489401A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 1982 |
| Grant date | Dec 18, 1984 |
| Priority date | — |
| Expiry date | Apr 12, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/781
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuitry for isolating and rendering inoperative faulty storage devices in a semiconductor memory array is disclosed. A determination is made as to whether the x-addresses of the faulty storage devices contain an address bit having a common value for all of the faulty storage devices. If such an address bit exists, the address buffer associated with the common address bit is programmed to lock in a permanent set of address indicator outputs. All x-address locations accessed by address signals containing the common address bit are thereafter disabled. The memory array continues to function at half its former storage capacity, using the storage devices associated with the remaining address locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.