Method of electrically testing a packaging structure having n interconnected integrated circuit chips

US4494066A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Prabhakar Goel · Poughkeepsie, US
• Maurice T. McMahon · Poughkeepsie, US

Key dates

• Filing date: Jul 29, 1983
• Grant date: Jan 15, 1985
• Expiry date: Jul 29, 2003

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/31855
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Design rules and test structure are used to implement machine designs to thereby obviate during testing the need for mechanical probing of the chip, multichip module, card or board at a higher level of package. The design rules and test structure also provide a means of restricting the size of logic partitions on large logical structures to facilitate test pattern generation. A test mechanism is available on every chip to be packaged to drive test data on all chip outputs and observe test data on all chip inputs, independent of the logic function performed by the chip. A control mechanism is also provided to allow a chip to either perform its intended function or to act as a testing mechanism during package test. It is intended that the test mechanism built into every chip will be used in place of mechanical probes to perform a chip-in-place test and interchip wiring test of the package. The intent of the design rules is to design chips such that each chip can be "isolated" for testing purposes through the pins (or other contacts) of a higher level package containing such chips. It is also required that the "Level Sensitive Scan Design" (LSSD) discipline, or rules, be followed for …