Substrate wiring patterns for connecting to integrated-circuit chips
US4495377A · kind A · utility
22Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1982 |
| Grant date | Jan 22, 1985 |
| Priority date | — |
| Expiry date | Dec 30, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An IC chip connects to a substrate by a pattern of pads arranged in single lines along the radial edges of segments of a polygon underlying the chip-linear conductors from the pads cross the outer edge of the segments in parallel groups. Wider power conductors can also be placed in the pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.