Charles L. Johnson
22Patents
11h-index
36Co-inventors
75Inventor score
Filing activity: Dec 30, 1982 → Jun 25, 2015
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8736068B2 | Hybrid bonding techniques for multi-layer semiconductor stacks | Electricity | 207 | Active |
| US5077676A | Reducing clock skew in large-scale integrated circuits | Electricity | 58 | Expired |
| US4939389A | VLSI performance compensation for off-chip drivers and clock generation | Electricity | 56 | Expired |
| US4857765A | Noise control in an integrated circuit chip | Electricity | 32 | Expired |
| US5371764A | Method and apparatus for providing an uninterrupted clock signal in a data processing system | Physics | 31 | Expired |
| US5790838A | Pipelined memory interface and method for using the same | Physics | 28 | Expired |
| US5235521A | Reducing clock skew in large-scale integrated circuits | Physics | 25 | Expired |
| US4495377A | Substrate wiring patterns for connecting to integrated-circuit chips | Electricity | 22 | Expired |
| US9495498B2 | Universal inter-layer interconnect for multi-layer semiconductor stacks | Electricity | 17 | Active |
| US5911063A | Method and apparatus for single phase clock distribution with minimal clock skew | Physics | 14 | Expired |
| US8445918B2 | Thermal enhancement for multi-layer semiconductor stacks | Electricity | 13 | Active |
| US8140297B2 | Three dimensional chip fabrication | Electricity | 11 | Active |
| US9245813B2 | Horizontally aligned graphite nanofibers in etched silicon wafer troughs for enhanced thermal performance | Electricity | 10 | Active |
| US5815694A | Apparatus and method to change a processor clock frequency | Physics | 10 | Expired |
| US6260164A | SRAM that can be clocked on either clock phase | Physics | 8 | Expired |
| US8293578B2 | Hybrid bonding techniques for multi-layer semiconductor stacks | Electricity | 8 | Active |
| US8127079B2 | Intelligent cache injection | Physics | 4 | Active |
| US8330489B2 | Universal inter-layer interconnect for multi-layer semiconductor stacks | Electricity | 3 | Active |
| US8367478B2 | Method and system for internal layer-layer thermal enhancement | Electricity | 2 | Active |
| US9111899B2 | Horizontally and vertically aligned graphite nanofibers thermal interface material for use in chip stacks | Electricity | 2 | Active |
| US9811287B2 | High-performance hash joins using memory with extensive internal parallelism | Physics | 1 | Active |
| US9817612B2 | High-performance hash joins using memory with extensive internal parallelism | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.