Apparatus for redundant operation of modules in a multiprocessing system
US4503534A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1982 |
| Grant date | Mar 5, 1985 |
| Priority date | — |
| Expiry date | Jun 30, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1675
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A number of intelligent nodes (bus-interface units-BIUs and memory-control units-MCUs) are provided in a matrix composed of processor buses (105) with corresponding error-reporting and control lines (106); and memory buses (107) with corresponding error-reporting and control lines (108). Each node (100, 101, 102, 103) has means for logging errors and reporting errors on the error-report lines (106, 108). Processor modules (110) and memory modules (112) are each connected to a node which controls access to a common memory bus (107). Each node includes means (a married bit-170 and a shadow bit-172) for marrying modules in pairs such that each module in the pair tracks the operations directed to the module pair, and each module in the pair alternates with the other module in the handling of requests or replies. Each node registers the ID of the other node in a spouse ID register. Comparison logic (162, 164) in each node resets the married bit upon the condition that the node ID (identifying the node at which the error occurred) in an error-report message is equal to the ID stored in the spouse ID register, thus identifying the spouse node (the partner of the node in which the comparis…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.