Method of forming a number of solder layers on a semiconductor wafer
US4503597A · kind A · utility
7Cited by
2References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 7, 1983 |
| Grant date | Mar 12, 1985 |
| Priority date | — |
| Expiry date | Feb 7, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a number of discrete solder layers on a semiconductor wafer of a large area. A number of regions which are easy to be wetted with solder are formed on one of the major surfaces of the wafer. A solder foil is positioned on the one major surface and a plate-like jig including a plate and projections formed on one surface thereof is disposed on the solder foil with the projections facing the latter. By heating the stacked assembly at a sufficiently high temperature for the solder foil to be molten, a number of the discrete solder layers having a uniform thickness are formed on the semiconductor wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.