Universal memory
US4513372A · kind A · utility
36Cited by
2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 15, 1982 |
| Grant date | Apr 23, 1985 |
| Priority date | — |
| Expiry date | Nov 15, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/407
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is disclosed that operates internally substantially independent of the timing of signals from its associated computer. That is, the timing controls for multiplexing the row and column address into the memory chips as well as the enabling signal for writing information into the chips are controlled by different delay lines so that the memory always operates at its optimal operational speed. In addition, the input and output latches are arranged to receive or output information to or from the computer at a time that is optimal for the computer or other information requester.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.