Programmable chip tester having plural pin unit buffers which each store sufficient test data for independent operations by each pin unit
US4517661A · kind A · utility
52Cited by
15References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 16, 1981 |
| Grant date | May 14, 1985 |
| Priority date | — |
| Expiry date | Jul 16, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31919
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test system for testing circuits in integrated circuit chips includes a host computer for controlling the test system, and a plurality of blocks operable in parallel and each including a controller, storage for test programs and test data, and plurality of electronic units or pin electronics cards, one unit being associated with one of the pins of a device under test. Each of the electronic units include timing circuitry for timing its associated pin independent of the timing of any other electronics unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.