Method of making EPROM cell with reduced programming voltage

US4519849A · kind A · utility

Assignee

• Intel Corporation · US

Inventors

• George J. Korsh · Redwood City, US
• Mark A. Holler · Palo Alto, US
• George Perlegos · Fremont, US
• Paolo Gargini · Palo Alto, US

Key dates

• Filing date: Jul 22, 1983
• Grant date: May 28, 1985
• Expiry date: Jul 22, 2003

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

An improved floating gate MOS EPROM cell which is programmable at a lower potential (12 volts) than prior art devices which often require 25 volts. The oxide thickness between the floating gate and overlying control gate is thicker at the edges of the floating gate than in the central portion. The thicker oxide at the edges prevents uncontrolled DC erasing. This allows a thinner oxide to be used in the central portion and provides the increased capacitance coupling needed for programming at a lower potential.