Bilevel resist
US4521274A · kind A · utility
21Cited by
2References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 24, 1984 |
| Grant date | Jun 4, 1985 |
| Priority date | — |
| Expiry date | May 24, 2004 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/95
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Excellent resolution in the lithographic fabrication of electronic devices is achieved with a specific bilevel resist. This bilevel resist includes an underlying layer formed with a conventional material such as a novolac resist baked at 200.degree. C. for 30 minutes and an overlying layer including a silicon containing material such as that formed by the condensation of formaldehyde with a silicon-substituted phenol. This bilevel resist has the attributes of a trilevel resist and requires significantly less processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.