Fault alignment control system and circuits
US4534029A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 1983 |
| Grant date | Aug 6, 1985 |
| Priority date | — |
| Expiry date | Mar 24, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This permutation circuit can be considered to be a multi-bit adder without a carry. In one embodiment it takes the form of m address bits being fed to m+y 2-way exclusive OR gates with m+y permutation bits to generate m+y input bits accessing a decoder with 2.sup.m output positions. In another embodiment the decoder takes the form an m bit adder with which adds m address bits to m permutation bits to generate m bit actual address. Multiple decoders of both types may be joined together in various combinations to generate higher order addresses. Also, k full-adder of less than m bits can also be used in similar fashion as m+y Exor gates to provide shift rotate capability within a desired block of 2.sup.y rows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.