Shanker Singh
21Patents
13h-index
13Co-inventors
78Inventor score
Filing activity: Jan 10, 1977 → Mar 29, 2002
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5233614A | Fault mapping apparatus for memory | Physics | 95 | Expired |
| US6449689B1 | System and method for efficiently storing compressed data on a hard disk drive | Physics | 80 | Expired |
| US4584681A | Memory correction scheme using spare arrays | Physics | 75 | Expired |
| US6360300B1 | System and method for storing compressed and uncompressed data on a hard disk drive | Physics | 63 | Expired |
| US6101624A | Method and apparatus for detecting and correcting anomalies in field-programmable gate arrays using CRCs for anomaly detection and parity for anomaly correction | Physics | 41 | Expired |
| US6324621A | Data caching with a partially compressed cache | Physics | 39 | Expired |
| US6785837B1 | Fault tolerant memory system utilizing memory arrays with hard error detection | Physics | 36 | Expired |
| US6105155A | Method and apparatus for performing on-chip function checks and locating detected anomalies within a nested time interval using CRCs or the like | Physics | 34 | Expired |
| US6799291B1 | Method and system for detecting a hard failure in a memory array | Physics | 21 | Expired |
| US4584682A | Reconfigurable memory using both address permutation and spare memory elements | Physics | 18 | Expired |
| US6178489A | Method and apparatus for managing linear address mapped storage under selective compression and regency of usage constraints | Physics | 16 | Expired |
| US5832005A | Fault-tolerant method and means for managing access to an initial program load stored in read-only memory or the like | Physics | 15 | Expired |
| US4485471A | Method of memory reconfiguration for fault tolerant memory | Physics | 14 | Expired |
| US6728156B2 | Memory array system | Physics | 13 | Expired |
| US5873126A | Memory array based data reorganizer | Physics | 11 | Expired |
| US6877046B2 | Method and apparatus for memory with embedded processor | Physics | 10 | Expired |
| US6546411B1 | High-speed radix 100 parallel adder | Physics | 8 | Expired |
| US6732291B1 | High performance fault tolerant memory system utilizing greater than four-bit data word memory arrays | Physics | 7 | Expired |
| US4118786A | Integrated binary-BCD look-ahead adder | Physics | 7 | Expired |
| US4534029A | Fault alignment control system and circuits | Physics | 6 | Expired |
| US5485588A | Memory array based data reorganizer | Physics | 2 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.