Method for manufacturing vertical PNP transistor with shallow emitter
US4534806A · kind A · utility
12Cited by
8References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 7, 1983 |
| Grant date | Aug 13, 1985 |
| Priority date | — |
| Expiry date | Mar 7, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28525
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A PNP semiconductor device and a manufacturing method therefore. In the method, a window is formed on the surface of a semiconductor substrate having an N-type base region formed therein. A polycrystalline layer is formed on the base region in the window. The polycrystalline silicon layer is ion implanted under specific predetermined conditions with a P-type doping ion. The P-type doping ion is diffused by an annealing treatment under predetermined conditions into the base region to form a shallow emitter region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.