CMOS process for fabricating integrated circuits, particularly dynamic memory cells with storage capacitors

US4536947A · kind A · utility

Assignee

• Intel Corporation · US

Inventors

• Mark Bohr · Beaverton, US
• Ken K. Yu · Portland, US
• Leo D. Yau · Portland, US
• Shyam Garg · Austin, US

Key dates

• Filing date: Jul 2, 1984
• Grant date: Aug 27, 1985
• Expiry date: Jul 2, 2004

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/911

Abstract

A CMOS process is described which is particularly suited for forming dynamic memory cells. The cells are formed in an n-well and a single plate member formed from a first layer of polysilicon is used for the entire array. Unique etching of the first polysilicon layer prevents stringers from occurring when the second layer of polysilicon is deposited. A tri-layer dielectric is used for the capacitors in the array. Novel "rear-end" processing is disclosed using a phosphorus doped glass.