Fabrication of junction field effect transistor with filled grooves

US4543706A · kind A · utility

Assignee

• GTE Laboratories Incorporated · US

Inventors

• Izak Bencuya · San Jose, US
• Adrian I. Cogan · Redwood City, US

Key dates

• Filing date: Feb 24, 1984
• Grant date: Oct 1, 1985
• Expiry date: Feb 24, 2004

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/343

Abstract

Junction field effect transistor, specifically a static induction transistor and method of fabricating. A low resistivity N-type layer is formed at the surface of a high resistivity N-type epitaxial layer which has been grown on a low resistivity N-type substrate of silicon. The surface of the low resistivity N-type layer is coated with silicon nitride, portions of the silicon nitride are removed, and the silicon is etched to form parallel grooves with interposed ridges of silicon. Silicon dioxide is grown in the grooves, removed from the end walls of the grooves, and P-type zones are formed at the end walls of the grooves. Metal contacts are applied to the P-type zones at the end walls of the grooves. The grooves are filled with filler material and materials are etched away to produce a flat, planar surface with low resistivity N-type silicon of the ridges exposed in the surface and with filler material in the grooves also exposed at the surface. A large area metal contact is applied which extends across the surface and makes ohmic contact to the low resistivity N-type silicon of all the ridges.