Random pattern self test design
US4546473A · kind A · utility
8Cited by
4References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 6, 1983 |
| Grant date | Oct 8, 1985 |
| Priority date | — |
| Expiry date | May 6, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1772
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLA is constructed to improve random testing. Section circuits are provided that permit disabling sections of the output lines that are called segments so that the circuit can be tested one segment at a time. Selection circuits are also provided for enabling the product term lines only one at a time. Thus, while random test signals are conventionally applied to the PLA input terminals for test, only a small portion of the PLA is enabled for the test. Control signals for the selection circuits are generated randomly so that the portion of the PLA that is tested is varied randomly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.