Trench-defined semiconductor structure
US4547793A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 27, 1983 |
| Grant date | Oct 15, 1985 |
| Priority date | — |
| Expiry date | Dec 27, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/184
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved device isolated by a trench formed in an N conductivity type semiconductor substrate is provided which has first and second spaced apart P conductivity type regions butted to a sidewall of the trench. An N+ doped region is disposed adjacent to the sidewall of the trench extending from the surface of the semiconductor substrate to an N+ buried region and interposed between the first and second P type conductivity regions. The dopant concentration in the N+ doped region is higher than that of the semiconductor substrate but not higher than the dopant concentration of the N+ buried region. More particularly, a lateral PNP transistor, isolated within a trench formed in an N type conductivity semiconductor substrate having an N+ buried region, has emitter and collector regions butted against a sidewall of the trench, along with the transistor's base region. A highly doped N+ base segment is disposed within the base region of the transistor adjacent to the sidewall of the trench extending from the surface of the substrate to the N+ buried region, and interposed between the emitter and collector regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.