Dram with polysi bit lines and added junction capacitance
US4551741A · kind A · utility
4Cited by
9References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1983 |
| Grant date | Nov 5, 1985 |
| Priority date | — |
| Expiry date | Dec 29, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having two layers of polycrystal silicon and having an insulated gate field effect transistor as a fundamental element including by using a first layer of polycrystalline silicon serving as an electrode of a capacitor and a bit line and a second layer of polycrystalline silicon serving as a gate electrode of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.