Method of fabricating junction field effect transistors

US4551909A · kind A · utility

Assignee

• GTE Laboratories Incorporated · US

Inventors

• Adrian I. Cogan · Redwood City, US
• Izak Bencuya · San Jose, US

Key dates

• Filing date: Mar 29, 1984
• Grant date: Nov 12, 1985
• Expiry date: Mar 29, 2004

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/343

Abstract

Junction field effect transistor, specifically a static induction transistor, and method of fabricating. A low resistivity N-type surface layer is formed at the surface of a high resistivity N-type epitaxial layer which has been grown on a low resistivity N-type substrate of silicon. The surface of the surface layer is coated with silicon dioxide and portions of the silicon dioxide layer are removed to expose alternating gate surface areas and source surface areas. P-type conductivity material is diffused into the silicon from the gate surface areas to produce zones of graded concentration. The difference in concentration of N-type conductivity imparting material in the surface layer and in the remainder of the epitaxial layer causes the resulting P-type gate regions to extend laterally toward each other so as to produce narrow channel regions at a depth beyond the surface layer while limiting the lateral extensions of the P-type gate regions adjacent to the surface. The device exhibits both high voltage gain and low gate capacitance.