Method of fabricating VLSI CMOS devices having complementary threshold voltages

US4555842A · kind A · utility

Assignee

• AT&T Bell Laboratories · US

Inventors

• Hyman J. Levinstein · Berkeley Heights, US
• Sheila Vaidya · Watchung, US

Key dates

• Filing date: Mar 19, 1984
• Grant date: Dec 3, 1985
• Expiry date: Mar 19, 2004

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S148/082

Abstract

For optimal performance, the threshold voltages V.sub.TP and V.sub.TN of the p- and n-channel transistors in a CMOS device should be the respective complements of each other. In polysilicon-gate devices, this can be achieved by adjusting the corresponding gate-metal work function utilizing p.sup.+ and n.sup.+ polysilicon for the respective gates of the p- and n-channel transistors. However, when a refractory metal silicide-over-polysilicon gate structure is employed in a VLSI CMOS device in which the gates of a pair of adjacent complementary transistors are connected together, an anomalously large negative V.sub.TP is measured. The invention is a unique process sequence that achieves substantially complementary p- and n-channel transistor thresholds in a high-speed VLSI CMOS device that includes silicide-over-polysilicon gates.