Vertically isolated complementary transistors
US4556585A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 1985 |
| Grant date | Dec 3, 1985 |
| Priority date | — |
| Expiry date | Jan 28, 2005 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/082
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for making complementary transistor devices in an epitaxial layer of a first conductivity type having a deep vertical isolation sidewall between the N and P channel transistors by providing a backfilled cavity in the epitaxial layer, the sidewalls of the cavity being coated with layers of material, the first layer being a silicate doped with the same conductivity type as the epitaxial layer in contact with the epitaxial layer and overcoated with an isolation and diffusion barrier layer, the second silicate layer doped to a conductivity opposite to that of the first layer and isolated therefrom by said isolation and diffusion barrier material. The cavity is backfilled with semiconductor material of a conductivity type opposite to that of the epitaxial layer and during this backfilling operation the dopants in the first and second layer outdiffuse into the epitaxial layer and into the backfill material respectfully to prevent the creations of parasitic channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.