Electrically-programmable and electrically-erasable MOS memory device
US4558344A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 29, 1982 |
| Grant date | Dec 10, 1985 |
| Priority date | — |
| Expiry date | Jan 29, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An MOS memory cell (44) including an electrically-programmable and electrically-erasable storage device (46) fabricated on a semiconductor substrate (50) is disclosed. The storage device (46) is divided into sensing and programming sections (90, 92), each of which sections comprises vertically-aligned floating gate and program gate portions (62L, 62R, 72L, 72R) respectively formed from first and second electrically-conductive strips (62, 72). A tunneling region (60) is formed in the substrate (50) beneath the floating gate portion (62R) of the storage device programming section (92) and a thin tunnel dielectric (70) is interposed between the tunneling region (60) and the programming section floating gate portion (62R to facilitate tunneling of charge carriers therebetween. First and second source/drain regions (94, 96) physically isolated from the tunneling region (60) are established in the substrate (50) in alignment with the sensing section floating gate and program gate portions (62L, 72L). The memory cell (44) additionally includes a selection device (48) comprised of first and second field effect transistor structures (98, 104) which can be activated during memory cell read, …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.