Method of manufacturing stable, low resistance contacts in integrated semiconductor circuits
US4562640A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 1984 |
| Grant date | Jan 7, 1986 |
| Priority date | — |
| Expiry date | Mar 22, 2004 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/019
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing stable, low resistance contacts in an integrated semiconductor circuit which involves providing highly doped impurity diffused regions in a silicon substrate, forming a silicon dioxide layer over the highly doped diffused regions and the surrounding substrate, forming contact holes of uniform size in the silicon dioxide layer in selected areas of the highly doped diffused regions, applying a layer including a metal silicide into the holes in contact with the underlying highly doped diffused regions, applying an n.sup.+ -doped polysilicon layer into the contact holes and over the silicon dioxide layer with a thickness corresponding to about half the contact hole side length, and then depositing a layer of predominantly aluminum over the n.sup.+ -doped polysilicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.