Connection verification between circuit board and circuit tester
US4563636A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 1983 |
| Grant date | Jan 7, 1986 |
| Priority date | — |
| Expiry date | Dec 12, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/70
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus and a method is provided for verifying electrical coupling between a first contact point of an electrical device on a circuit board and a first connection pin, on a board tester. Within the tester, a JK flip-flop is electrically coupled to the first connection pin through an amplifier. A Q output of the JK flip-flop is initialized to a logic 0. An electrical probe with an electrical voltage is stroked across the first contact point and any other contact points on the circuit. If the first contact point is electrically coupled to the first connection pin, a logic 1 will be held on the Q output of the JK flip-flop. If there is no electrical coupling, then a logic 0 will be held on the Q output. By reinitializing the JK flip-flop and electrically coupling it to another connection pin, electrical coupling between another contact point and another connection pin may be tested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.