Data processor which can repeat the execution of instruction loops with minimal instruction fetches
US4566063A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 1983 |
| Grant date | Jan 21, 1986 |
| Priority date | — |
| Expiry date | Oct 17, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pipelined data processor capable of automatically storing in an external memory all essential information relating to the internal state thereof upon the detection of an access fault during instruction execution. Upon correction of the cause of the fault, the data processor automatically retrieves the stored state information and restores the state thereof in accordance with the retrieved state information. The data processor then resumes execution of the instruction. The faulted access may be selectively rerun upon the resumption of instruction execution. In response to detecting a particular sequence of a loopable instruction followed by a conditional branch instruction which selectively branches back to the loopable instruction, the data processor enters a loop mode wherein the loopable instruction and the branch instruction are internally recirculated around the pipeline to save instruction fetch cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.