Method of fabricating a static induction type recessed junction field effect transistor

US4566172A · kind A · utility

Assignee

• GTE Laboratories Incorporated · US

Inventors

• Izak Bencuya · San Jose, US
• Adrian I. Cogan · Redwood City, US

Key dates

• Filing date: Feb 24, 1984
• Grant date: Jan 28, 1986
• Expiry date: Feb 24, 2004

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/343

Abstract

Junction field effect transistor, specifically a static induction transistor and method of fabricating. A low resistivity N-type layer is formed at the surface of a high resistivity N-type epitaxial layer which has been grown on a low resistivity N-type substrate of silicon. The surface of the low resistivity N-type layer is coated with silicon nitride, portions of the silicon nitride are removed and the silicon is etched to form parallel grooves with interposed ridges of silicon. Silicon dioxide is grown in the grooves, removed from the end walls of the grooves, and P-type zones are formed at the end walls of the grooves. The depth of the grooves is increased by etching to remove most of the P-type zone underlying each groove while leaving laterally extending P-type portions. Oxygen is implanted to convert the remainder of the P-type zones underlying the end walls of the grooves to silicon dioxide. Metal layers are deposited in the bottoms of the grooves making contact with the P-type portions. The grooves are filled with filler material and materials are etched away to produce a flat, planar surface with low resistivity N-type silicon of the ridges exposed in the surface and with…