Use of an electronic vernier for evaluation of alignment in semiconductor processing
US4566193A · kind A · utility
15Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 1984 |
| Grant date | Jan 28, 1986 |
| Priority date | — |
| Expiry date | Jul 31, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01B7/31
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An electronic vernier is presented which detects and quantifies misalignment between layers of material deposited upon a semiconducting wafer. Verniers may be constructed which evaluate alignment between two conducting layers, between two conducting layers and an insulating layer and between a semiconducting layer and a capacitive layer. Circuitry is described which shows how output from a vernier may be detected and quantified in order to evaluate the amount of misalignment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.