Method and apparatus for memory overlay
US4569048A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 19, 1983 |
| Grant date | Feb 4, 1986 |
| Priority date | — |
| Expiry date | Sep 19, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2236
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor-based system (10) is tested by a testing device (32) that substitutes instructions from a substitute memory (38) for those in the main memory (28) of the system (10) under test. When the processor (12) of the system under test attempts to read a location in its memory (28), it places signals on bus address lines (22) to designate the memory location and places a data-direction signal on a control line (50) to indicate that the memory (28) is to transmit rather than receive information. In ordinary operation, the memory then places its data on bus data lines (24). In order to replace the data from the main memory (28) with data from the substitute memory (38), the testing device (32) senses whether the address lines (22) carry the address of a memory location whose contents are to be substituted. When such an address is detected, it overdrives the control line (50) to cause it to indicate a write rather than a read. This prevents the main memory (28) from placing its data on the data lines (24). Instead, the test device (32) causes its substitute memory (38) to place its contents on the data lines (24). Since there is no contention between the substitute memory (38)…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.